1. Field of the Invention
This invention relates to the layout of interconnect lines within integrated circuits, and more specifically relates to the layout of one or more pairs of differential signal lines upon an integrated circuit.
2. Description of Related Art
As horizontal dimensions used in the layout of integrated circuits have decreased, the affect of lateral parasitic capacitance on the loading of various interconnection lines has consequently increased. This is particularly true with long interconnections, such as are typically encountered, for example, in the array of a static RAM (SRAM). In an SRAM array, neighboring signal lines can impact the signal strength of each bitline pair due to the capacitive coupling of undesired signals from the neighboring signal lines. This can cause slow or pattern dependent access times for fully static devices or, if the data is latched, it can cause wrong data to be latched. As an example, FIG. 1 shows a small portion of a representative single port SRAM array showing one wordline (also known as a row line) and three bitline pairs. A first bitline BL10, and its corresponding complement bitline XBL10, together form the first bitline pair. Bitlines BL11 and XBL11 together form the second bitline pair, and bitlines BL12 and XLB12 form the third bitline pair. A single wordline RLX addresses three memory cells, S10, S11, and S12 which are respectively associated with bitline pairs BL10/XBL10, BL11/XBL11, and BL12/XBL12. Bitline load L10 is connected to both BL10 and XBL10 (which may also be collectively known as bitline 10). Likewise bitline load L11 and bitline load L12 are respectively connected to bitline pairs BL11/XBL11 and BL12/XBL12. Sense amp SA11, sense amp SA12 and sense amp SA13 are respectively coupled to bitline pairs BL10/XBL10, BL11/XBL11, and BL12/XBL12. A capacitor CBL10 represents the total capacitive load from bitline BL10 to all structures other than the individual bitlines adjacent to bitline BL10. Likewise, capacitor CXBL10 represents the total capacitive load on bitline XBL10 with the same exception of the capacitance to individual adjacent bitlines. The capacitance on a given bitline may be represented by a single lumped capacitor, such as capacitor CBL10, even though the total capacitance actually includes a number of individual capacitors, each connected between the bitline and a neighboring or overlapping structure. Similarly, capacitors CBL11, CXBL11, CBL12, and CXBL12 represent a corresponding capacitive load on bitlines BL11, XBL11, BL12, and XBL12, respectively. Capacitors CC1, CC2, CC3, CC4, CC5, CC6 and CC7 represent capacitive loading from a given bitline to an adjacent bitline. For example, capacitor CC3 represents the lateral parasitic capacitance between bitlines XBL10 and BL11. As a further example, capacitor CC6 represents the lateral parasitic capacitance between bitlines BL12 and XBL12. Capacitor CC1 represents the lateral parasitic capacitance between bitline BL10 and a line (not shown) running adjacent to bitline BL10. Likewise, capacitor CC7 represents a similar lateral parasitic capacitance between bitline XBL12 and a line (or other interconnection, not shown) running adjacent to bitline XBL12.
A variety of SRAM configurations are possible. For example, if the SRAM array depicted in FIG. 1 is dynamically precharged, both bitlines of a bitline pair are typically precharged high. When a wordline is enabled, one bitline, either the true or the complement bitline, is driven low by the addressed memory cell. Such a bitline is usually never driven all the way to ground potential due to the bitline load structures. In other configurations, both bitlines may equilibrate to an intermediate level and the activation of a wordline may cause one bitline to be actually driven high while the other is driven low. For the purposes of this discussion, one can generalize that for a given bitline pair, one bitline is driven high while the other bitline is driven low whenever a memory cell is addressed by an active wordline.
Further for the purposes of this discussion, we can assume that the polarity convention of the bitlines is such that when a logic "1" is read from a memory cell, for example memory cell S10, bitline BL10 remains high or is driven high (toward VDD) and bitline XBL10 is driven low (toward VSS or ground). Conversely, when a logic "0" is read from memory cell S10, bitline XBL10 remains high and bitline BL10 is driven toward ground. This choice is entirely arbitrary but is consistent with that frequently encountered in the art. An example of the effect of neighboring signal lines on a given bitline can be seen by assuming that the memory cells S10, S11 and S12 all contain a logic "0". When wordline RLX is activated, the true bitlines BL10, BL11 and BL12 are all driven toward ground and the complement bitlines XBL10, XBL11 and XBL12 are all driven high or remain high, depending on design choices in the SRAM configuration.
In the "0", "0", "0" data pattern example described above, bitline BL11 is driven low and is surrounded by bitlines XBL10 an XBL11, both of which are driven high. Consequently, coupling capacitors CC3 and CC4 tend to impart a positive voltage transition on bitline BL11 which is opposite in direction to the low-going transition caused by the reading of the logic "0" within memory cell S11. Furthermore, bitline XBL11 is driven high by the reading of memory cell S11 and is surrounded by bitlines BL11 and BL12, which are actively driven low and which couple a negative-going voltage onto bitline XBL11. The net effect of the lateral coupling from bitlines XBL10 and BL12 into both bitlines BL11 and XBL11 tends to delay the development of the intended differential voltage conveyed on bitlines BL11 and XBL11, and thus delays the successful readout of memory cell S11. This would, of course, result in an access time penalty which is data-dependent. Such an impact is dependent upon the bitline spacings, oxide thickness, metal line thickness, the cell currents, the elapsed time, and other variables generally known in the art. These unwanted capacitive effects can either delay or advance the signal differential between bitlines BL11 and XBL11 which again further leads to pattern dependent access time. For example, if memory cells S10 and S12 each contained a logic "1", then the differential signal conveyed on bitlines BL11 and XBL11 is increased by capacitive coupling through capacitors CC3 and CC5. Such an effect is highly undesirable in a SRAM array. Further, if an array is latched, such an effect may lead to incorrect functionality rather than merely an access time dependency.